![Speaker Photo](/sites/default/files/styles/content_width_mobile_min/public/uploads/tsujaeking.gif?itok=a2M7gmUR)
As the minimum feature size of an integrated circuit has been scaled down well below the wavelength of light used in the photolithographic process, the semiconductor industry has faced a growing challenge of continuing to increase the density of transistors at ever lower cost per transistor. This talk will describe a cost-effective method for defining sub-lithographic features, to help extend the era of Moore’s Law.
This content is restricted to our MIG members and members of the MIT community. Please login or contact us for more information about our partner programs.
This content is restricted to our MIG members and members of the MIT community. Please login or contact us for more information about our partner programs.